STK22C48
Document Number: 001-51000 Rev. **
Page 2 of 14
Pin Configurations
Figure 1. Pin Diagram - 28-Pin SOIC
Table 1. Pin Definitions
Pin Name
Alt
IO Type
Description
A0–A10
Input
Address Inputs. Used to select one of the 2,048 bytes of the nvSRAM.
DQ0-DQ7
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
WE
W
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
CE
E
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
G
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
VSS
Ground
Ground for the Device. The device is connected to ground of the system.
VCC
Power Supply Power Supply Inputs to the Device.
HSB
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
VCAP
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
NC
No Connect
No Connect. This pin is not connected to the die.
VCAP
A7
A6
A5
A4
VCC
HSB
WE
A8
A9
OE
A10
DQ6
DQ7
DQ5
CE
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VSS
DQ0
A3
A2
A1
A0
DQ1
DQ2
28-SOIC
Top View
(Not To Scale)
NC
NC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
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