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STK11C88
Document Number: 001-50591 Rev. **
Page 11 of 15
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [11, 12]
Parameter
Alt
Description
25 ns
45 ns
Unit
Min
Max
Min
Max
tRC
tAVAV
STORE/RECALL Initiation Cycle Time
25
45
ns
tSA
[11]
tAVEL
Address Setup Time
0
0
ns
tCW
[11]
tELEH
Clock Pulse Width
20
30
ns
tHACE
[11]
tELAX
Address Hold Time
20
20
ns
tRECALL
[11]
RECALL Duration
20
20
μs
Switching Waveforms
Figure 10. CE Controlled Software STORE/RECALL Cycle [12]
tRC
tRC
tSA
tSCE
tHACE
tSTORE / tRECALL
DATA VALID
DATA VALID
6
#
S
S
E
R
D
D
A
1
#
S
S
E
R
D
D
A
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
Notes
11. The software sequence is clocked on the falling edge of CE without involving OE (double clocking abort the sequence).
12. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
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