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STAR1000 bảng dữ liệu(PDF) 9 Page - Cypress Semiconductor

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STAR1000
Document Number: 38-05714 Rev. *C
Page 9 of 21
Figure 5. Line Selection and Reset Sequence
Latching in a Y- address selects the addressed row and connects
the pixel outputs of that row to the column amplifiers. Through
the sequence of the S and R pulse and the reset pulse in
between the pixel output signal and reset level are sampled and
produced at the output of the column amplifier (to do the FPN
double sampling correction).
At this time horizontal read out of the selected row is started and
another row is reset to effectuate reduced integration time
(electronic rolling shutter).
A0......A9
LD_Y
INTERNAL
S
RESET
R
CAL
(Once each
frame)
ROW
READOUT
Read Address
Reset Address
k
l
m
k
l
m
Row Selected for Readout
Row Selected for Reset
a
b
c
d
e
b
hi
f
d
g
Time Available for Readout of Row Y-1
Idle
Time Available for X-readout of Row Y
Table 6. Timing Constraints of Line Sequence
Symbol
Min
Typ
Description
a3.6
μs
Delay between selection of a new row and falling edge on S.
Minimal value: For maximum, speed a new row can already be selected
during X- read out of the previous row.
b0.4
μs
Duration of S and R pulse.
c
0
100 ns
Delay between falling edge of S and rising edge of reset.
d
200 ns
Minimum duration of reset pulse.
[+] Feedback


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