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ISL12082IUZ bảng dữ liệu(PDF) 10 Page - Intersil Corporation |
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ISL12082IUZ bảng dữ liệu(HTML) 10 Page - Intersil Corporation |
10 / 26 page 10 FN6731.3 November 24, 2008 The ISL12082 has the ReSeal™ function, which allows the device to enter into the InterSeal™ Battery Saver mode after manufacture testing for board functionality. To use the ReSeal™ function, simply set RESEAL bit to “1” (address 07h) after the testing is completed. It will enable the InterSeal™ Battery Saver mode and prevents battery current drain before it is first used. Real Time Clock Operation The Real Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of sub-second, second, minute, hour, day of week, date, month, and year. The RTC also has leap-year correction. The RTC also corrects for months having fewer than 31 days and has a bit that controls 24 hour or AM/PM format. When the ISL12082 powers up after the loss of both VDD and VBAT, the clock will not begin incrementing until at least one byte is written to the clock register. Accuracy of the Real Time Clock The accuracy of the Real Time Clock depends on the frequency of the quartz crystal that is used as the time base for the RTC. Since the resonant frequency of a crystal is temperature dependent, the RTC performance will also be dependent upon temperature. The frequency deviation of the crystal is a function of the turnover-temperature of the crystal from the crystal’s nominal frequency. For example, a ~20ppm frequency deviation translates into an accuracy of ~1 minute per month. These parameters are available from the crystal manufacturer. The ISL12082 provides on-chip crystal compensation networks to adjust load capacitance to tune oscillator frequency from -94ppm to +140ppm. For more detailed information, see “Application Section” on page 22. Single Event and Interrupt The alarm mode is enabled via the ALME bit (address 08h). Choosing single event or interrupt alarm mode is selected via the IM bit (address 08h). Note that when the frequency output function is enabled, the alarm function is disabled. The standard alarm allows for alarms of time, date, day of the week, month, and year. When a time alarm occurs in single event mode, an IRQ1/fOUT and/or IRQ2 pin will be pulled low and the alarm status bit (ALM) will be set to “1”. The pulsed interrupt mode allows for repetitive or recurring alarm functionality. Hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and present time. Thus, it will alarm as often as every minute (if only the nth second is set) or as infrequently as once a year (if at least the nth month is set). During pulsed interrupt mode, the IRQ1/fOUT and/or IRQ2 pin will be pulled low for 210ms and the alarm status bit (ALM) will be set to “1”. Note: The ALM bit can be reset by the user or cleared automatically using the auto reset mode (see ARST bit, address 07h). The alarm function can be enabled/disabled during battery backup mode using the FOBATB bit (address 08h). For more information on the alarm, see “Alarm Registers” on page 14. Frequency Output Mode The ISL12082 has the option to provide a frequency output signal using the IRQ/fOUT pin. The frequency output mode is set by using the FO bits to select 4 possible output frequency values from 1kHz to 32.768kHz. The frequency output can be enabled/disabled during battery backup mode using the FOBATB bit (address 08h). I2C Serial Interface The ISL12082 has an I2C serial bus interface that provides access to the control and status registers and the user SRAM. The I2C serial interface is compatible with other industry I2C serial bus protocols using a bi-directional data signal (SDA) and a clock signal (SCL). Oscillator Compensation The ISL12082 provides the option of timing correction due to temperature variation of the crystal oscillator for either manufacturing calibration or active calibration. The total possible compensation is typically -94ppm to +140ppm. Two compensation mechanisms that are available are as follows: 1. An analog trimming (ATR) register that can be used to adjust individual on-chip digital capacitors for oscillator capacitance trimming. The individual digital capacitor is selectable from a range of 9pF to 40.5pF (based upon 32.758kHz). This translates to a calculated compensation of approximately -34ppm to +80ppm. See “ATR description” on page 22. 2. A digital trimming register (DTR) that can be used to adjust the timing counter by -63ppm to +126ppm. See “DTR description” on page 22. Also provided is the ability to adjust the crystal capacitance when the ISL12082 switches from VDD to battery backup mode. Register Descriptions The battery-backed registers are accessible following a slave byte of “1101111x” and reads or writes to addresses [00h:1Fh]. The defined addresses and default values are described in Table 1. Address 16h to 1Eh are not used. Reads or writes to addresses 16h to 1Eh will not affect operation of the device but should be avoided. Register Access The contents of the registers can be modified by performing a byte or a page write operation directly to any register address. The registers are divided into 4 sections. These are: 1. Real Time Clock (8 bytes): Address 00h to 06h, and 1Fh, with address 1Fh as read-only byte. 2. Control and Status (5 bytes): Address 07h to 0Bh. ISL12082 |
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