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UC1827-2 bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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UC1827-2 bảng dữ liệu(HTML) 7 Page - Texas Instruments |
7 / 15 page www.ti.com APPLICATION INFORMATION + – RT CT SYNC S R VREF 2.5 V OSCILLATOR VREF 10 kW 1.4 V 2.5 V 2.9 V 0.5 V RT CT VDG−99086 CIRCUIT BLOCK DESCRIPTION PWM Oscillator I RT + 2.5 V R RT (1) UC1827-1, UC1827-2 UC2827-1, UC2827-2 UC3827-1, UC3827-2 SLUS365A – APRIL 1999 – REVISED AUGUST 2005 Figure 1. Oscillator Block With External Connections The oscillator block diagram with external connections is shown in Equation 1. A resistor (RT) connected to pin RT sets the linear charge current: The timing capacitor (CCT) is linearly charged with the charge current forcing the OSC pin to charge to a 3.4 V threshold. After exceeding this threshold, the RS flip-flop is set driving CLKSYN high and RDEAD low which discharges CCT. CT continues to discharge until it reaches a 0.5 V threshold and resets the RS flip-flop which repeats the charging sequence as shown in Figure 2 As shown in Figure 3, several oscillators are synchronized to the highest free running frequency by connecting 100 pF capacitors in series with each CLKSYN pin and connecting the other side of the capacitors together forming the CLKSYN bus. The CLKSYN bus is then pulled down to ground with a resistance of approximately 10k. Referring to Figure 1, the synchronization threshold is 1.4 V. The oscillator blanks any synchronization pulse that occurs when OSC is below 2.5 V. This allows units, once they discharge below 2.5 V, to continue through the current discharge and subsequent charge cycles whether or not other units on the CLKSYN bus are still synchronizing. This requires the frequency of all free running oscillators to be within 17% of each other to assure synchronization. 7 |
Số phần tương tự - UC1827-2 |
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Mô tả tương tự - UC1827-2 |
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