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UC1525AQ bảng dữ liệu(PDF) 1 Page - Texas Instruments |
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UC1525AQ bảng dữ liệu(HTML) 1 Page - Texas Instruments |
1 / 9 page UC1525A/27A UC2525A/27A UC3525A/27A Regulating Pulse Width Modulators FEATURES • 8 to 35V Operation • 5.1V Reference Trimmed to ±1% • 100Hz to 500kHz Oscillator Range • Separate Oscillator Sync Terminal • Adjustable Deadtime Control • Internal Soft-Start • Pulse-by-Pulse Shutdown • Input Undervoltage Lockout with Hysteresis • Latching PWM to Prevent Multiple Pulses • Dual Source/Sink Output Drivers 15 12 3 6 5 7 9 1 2 8 10 Reference Regulator 16 UVLO Lockout 4 OSC 3kΩ 5kΩ 50 µA PWM Latch Flip Flop 13 14 11 13 11 14 UC1527A Output Stage UC1525A Output Stage COMP S S R +VIN GROUND SYNC RT CT DISCHARGE COMPENSATION INV INPUT NI INPUT SOFTSTART SHUTDOWN OUTPUT B OUTPUT A VC OUTPUT B OUTPUT A VC NOR NOR OR OR V REF Error Amp VREF OSC OUT To internal circuitry BLOCK DIAGRAM SLUS191B - February 1997 - Revised June 2005 DESCRIPTION The UC1525A/1527A series of pulse width modulator integrated circuits are de- signed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip +5.1V ref- erence is trimmed to ±1% and the input common-mode range of the error ampli- fier includes the reference voltage, eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchro- nized to an external system clock. A single resistor between the CT and the dis- charge terminals provides a wide range of dead-time adjustment. These devices also feature built-in soft-start circuitry with only an external timing ca- pacitor required. A shutdown terminal controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input volt- ages. This lockout circuitry includes approximately 500mV of hysteresis for jit- ter-free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulse has been terminated for any reason, the out- puts will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200mA. The UC1525A output stage features NOR logic, giving a LOW output for an OFF state. The UC1527A utilizes OR logic which results in a HIGH output level when OFF. |
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