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TL16PIR552PH bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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TL16PIR552PH bảng dữ liệu(HTML) 7 Page - Texas Instruments |
7 / 52 page TL16PIR552 DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RCV FIFO Serial to Parallel Flow Control XMT FIFO Parallel to Serial Flow Control Parallel to Serial Flow Control Serial to Parallel Flow Control XMT FIFO RCV FIFO UART1 UART2 D7 – D0 SINx SOUTx RTSx CTSx SOUTx SINx CTSx RTSx D7 – D0 Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example auto-RTS (see Figure 1) Auto-RTS data-flow control originates in the receiver timing and control block (see functional block diagram) and is linked to the programmed receiver-FIFO trigger level. When the receiver-FIFO level reaches a trigger level of 1, 4, or 8 (see Figure 3), RTSx is deasserted. With trigger levels of 1, 4, and 8, the sending UART may send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the deassertion of RTSx until after it has begun sending the additional byte. RTSx is automatically reasserted once the receiver (RCV) FIFO is emptied by reading the receiver buffer register(RBR). If the trigger level is 14 (see Figure 6), RTSx is deasserted after the first data bit of the sixteenth character is present on the SINx line. RTSx is reasserted when the RCV FIFO has at least one available byte space. auto-CTS (see Figure 1) The transmitter circuitry checks CTSx before sending the next data byte. When CTSx is active, it sends the next byte. To stop the transmitter from sending the following byte, CTSx must be released before the middle of the last stop bit that is currently being sent (see Figure 2). The auto-CTS function reduces interrupts to the host system. When flow control is enabled, the CTSx level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result. enabling autoflow control and auto-CTS Autoflow control is enabled by setting modem-control register (MCR) bit 5 (autoflow enable or AFE) and bit 1 (RTS) to 1. Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the MCR should be reset to 0 (this assumes a control signal is driving CTSx). auto-CTS and auto-RTS functional timing Start Bits 0 – 7 Start Bits 0 – 7 Start Bits 0 – 7 Stop Stop Stop SOUTx CTSx NOTE A: When CTSx is low, the transmitter keeps sending serial data out. When CTSx goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does not send the next byte. When CTSx goes from high to low, the transmitter begins sending data again. Figure 2. CTS Functional Timing |
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