TL16C552AMPN datasheet(10/39 Pages) TI

tên linh kiện	TL16C552AMPN

Giải thích chi tiết về linh kiện	DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

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TL16C552A, TL16C552AM

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

10

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

parallel port timing requirements over recommended ranges of supply voltage and operating

free-air temperature (see Note 16 and Figures 15, 16, and 17)

MIN

MAX

UNIT

tsu7

Setup time, data valid before STB

↓

1

µs

th6

Hold time, data valid after STB

↑

1

µs

tw6

Pulse duration, STB

↓

1

µs

td10

Delay time, BUSY

↑ to ACK ↓

Defined by printer

td11

Delay time, BUSY

↓ to ACK ↓

Defined by printer

tw7

Pulse duration, BUSY

↑

Defined by printer

tw8

Pulse duration, ACK

↓

Defined by printer

td12

Delay time, BUSY

↑ after STB ↑

Defined by printer

td13

Delay time, INT2

↓ after ACK ↓ (see Note 17)

22

ns

td14

Delay time, INT2

↑ after ACK ↑ (see Note 17)

20

ns

td15

Delay time, INT2

↑ after ACK ↑ (see Note 17)

24

ns

td16

Delay time, INT2

↓ after IOR ↑ (see Note 17)

25

ns

NOTES: 16. These parameters are not production tested.

17. td13 –td16 are all measured with a 15-pF load.

PARAMETER MEASUREMENT INFORMATION

2 V

0.8 V

CLK (XTAL1)

tw1

tw2

fclock = 16 MHz MAX

2 V

0.8 V

Figure 1. CLK Voltage Waveform

Device Under Test

680

Ω

82 pF

(see Note A)

2.54 V

TL16C552A

NOTE A: This includes scope and jig capacitance.

Figure 2. Output Load Circuit

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