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TL16C752 bảng dữ liệu(PDF) 10 Page - Texas Instruments

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TL16C752
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS305 – MAY 1999
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional description (continued)
Table 4. Interrupt Control Functions
IIR[5–0]
PRIORITY
LEVEL
INTERRUPT
TYPE
INTERRUPT SOURCE
INTERRUPT RESET METHOD
000001
None
None
None
None
000110
1
Receiver line
status
OE, FE, PE, or BI errors occur in characters in
the RX FIFO
FE< PE< BI: All erroneous characters are read
from the RX FIFO.
OE: Read LSR
001100
2
RX timeout
Stale data in RX FIFO
Read RHR
000100
2
RHR interrupt
DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level (FIFO enable)
Read RHR
000010
3
THR interrupt
TFE (THR empty)
(FIFO disable)
TX FIFO passes below trigger level (FIFO
enable)
Read IIR OR a write to the THR
000000
4
Modem status
MSR[3:0]/= 0
Read MSR
010000
5
Xoff interrupt
Receive Xoff character(s)/special character
Receive Xon character(s)/Read of IIR
100000
6
CTS, RTS
RTS pin or CTS pin change state from active
(low) to inactive (high)
Read IIR
It is important to note that for the receiver line status interrupt, it is LSR[7] which generates the interrupt.
LSR[4–2] are set when an erroneous character is read from the RX FIFO and they are cleared on a read of the
LSR. LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more
errors remaining in the FIFO.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon
flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read
of the ISR.
interrupt mode operation
In FIFO interrupt mode (FCR=1, IER[3:0] = 1) the processor is informed of the status of the receiver and
transmitter by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line stats register
(LSR) to see if any interrupts need to be serviced. Figure 5 shows FIFO interrupt mode operation.
1
1
1
1
IER
IIR
THR
RHR
IOW/IOR
INT
Processor
Figure 5. FIFO Interrupt Mode Operation


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