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SN74ACT3641PCB bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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SN74ACT3641PCB bảng dữ liệu(HTML) 11 Page - Texas Instruments |
11 / 26 page SN74ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mailbox registers Two 36-bit bypass registers are on the SN74ACT3641 to pass command and control information between port A and port B. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. A low-to-high transition on CLKA writes A0 – A35 data to the mail1 register when a port A write is selected by CSA, W/RA, and ENA with MBA high. A low-to-high transition on CLKB writes B0 – B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB with MBB high. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while its mail flag is low. When the port-B data (B0 – B35) outputs are active, the data on the bus comes from the FIFO output register when the port-B mailbox select (MBB) input is low and from the mail1 register when MBB is high. Mail2 data is always present on the port-A data (A0 – A35) outputs when they are active. The mail1 register flag (MBF1) is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB with MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A read is selected by CSA, W/RA, and ENA with MBA high. The data in a mail register remains intact after it is read and changes only when new data is written to the register. tpd(R-F) CLKA CLKB RST 0,1 th(FS) tsu(FS) th(RS) tsu(RS) FS1, FS0 IR tpd(C-IR) tpd(C-IR) OR tpd(C-OR) tpd(R-F) AE AF MBF1, MBF2 tpd(R-F) Figure 1. FIFO Reset Loading X and Y With a Preset Value of Eight |
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