SN74ABT3613

64

× 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

10

POST OFFICE BOX 655303

dynamic bus sizing

The port-B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from the

FIFO. Word- and byte-size bus selections can utilize the most-significant bytes of the bus (big endian) or

least-significant bytes of the bus (little endian). Port-B bus size can be changed dynamically and synchronous

to CLKB to communicate with peripherals of various bus widths.

The levels applied to the port-B bus-size select (SIZ0, SIZ1) inputs and the big-endian select (BE) input are

stored on each CLKB low-to-high transition. The stored port-B bus-size selection is implemented by the next

rising edge on CLKB according to Figure 1.

Only 36-bit long-word data is written to or read from the FIFO memory on the SN74ABT3613. Bus-matching

operations are done after data is read from the FIFO RAM. Port-B bus sizing does not apply to mail-register

operations.

Read From FIFO

Write to FIFO

(a) LONG-WORD SIZE

1st: Read From FIFO

2nd: Read From FIFO

(b) WORD SIZE – BIG ENDIAN

BYTE ORDER ON PORT A:

A35

A27

A26

A18

A17

A9

A8

A0

B35

B27

B26

B18

B17

B9

B8

B0

XL

L

BE

SIZ1

SIZ0

AB

CD

AB

CD

AB

CD

B35

B27

B26

B18

B17

B9

B8

B0

B35

B27

B26

B18

B17

B9

B8

B0

LL

H

BE

SIZ1

SIZ0

1st: Read From FIFO

2nd: Read From FIFO

(c) WORD SIZE – LITTLE ENDIAN

CD

AB

B35

B27

B26

B18

B17

B9

B8

B0

B35

B27

B26

B18

B17

B9

B8

B0

HL

H

BE

SIZ1

SIZ0

Figure 1. Dynamic Bus Sizing