SN74ABT3611

64

× 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCBS127E – JULY 1992 – REVISED APRIL 1998

9

POST OFFICE BOX 655303

almost-empty flag (AE)

The FIFO almost-empty flag is synchronized to the port clock that reads data from its array (CLKB). The

almost-empty state is defined by the value of the almost-full and almost-empty offset register (X). This register

is loaded with one of four preset values during a device reset (see

reset). AE is low when the FIFO contains

X or fewer words in memory and is high when the FIFO contains (X + 1) or more words.

Two low-to-high transitions on the port-B clock (CLKB) are required after a FIFO write for the almost-empty flag

to reflect the new level of fill. The almost-empty flag (AE) of a FIFO containing (X + 1) or more words remains

low if two CLKB cycles have not elapsed since the write that filled the memory to the (X + 1) level. AE is set high

by the second CLKB low-to-high transition after the FIFO write that fills memory to the (X + 1) level. A low-to-high

fills the FIFO to (X + 1) words. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle

(see Figure 6).

almost-full flag (AF)

The FIFO almost-full flag is synchronized to the port clock that writes data to its array (CLKA). The almost-full

state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with

one of four preset values during a device reset (see

reset). AF is low when the FIFO contains (64 – X) or more

words in memory and is high when the FIFO contains [64 – (X + 1)] or fewer words.

Two low-to-high transitions on the port-A clock (CLKA) are required after a FIFO read for AF to reflect the new

level of fill. The almost-full flag of a FIFO containing [64 – (X + 1)] or fewer words remains low if two CLKA cycles

have not elapsed since the read that reduced the number of words in memory to [64 – (X + 1)]. AF is set high

by the second CLKA low-to-high transition after the FIFO read that reduces the number of words in memory

or greater, after the read that reduces the number of words in memory to [64 – (X + 1)]. Otherwise, the

subsequent CLKA cycle can be the first synchronization cycle (see Figure 7).

mailbox registers

Two 36-bit bypass registers are on the SN74ABT3611 to pass command and control information between port

A and port B. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a

port-data-transfer operation. A low-to-high transition on CLKA writes A0 – A35 data to the mail1 register when

a port-A write is selected by(CSA, W/RA, and ENA) with MBA high. A low-to-high transition on CLKB writes

B0 – B35 data to the mail2 register when a port-B write is selected by (CSB, W/RB, and ENB) with MBB high.

Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register

are ignored while its mail flag is low.

When the port-B data (B0 – B35) outputs are active, the data on the bus comes from the FIFO output register

when MBB is low and from the mail1 register when MBB is high. Mail2 data is always present on A0 – A35 outputs

when they are active. The mail1 register flag (MBF1) is set high by a low-to-high transition on CLKB when a

port-B read is selected by CSB, W/RB, and ENB with MBB high. The mail2 register flag (MBF2) is set high by

a low-to-high transition on CLKA when a port-A read is selected by CSA, W/RA, and ENA with MBA high. The

data in a mail register remains intact after it is read and changes only when new data is written to the register.

parity checking

The port-A (A0 – A35) inputs and port-B (B0 – B35) inputs each have four parity trees to check the parity of

incoming (or outgoing) data. A parity failure on one or more bytes of the input bus is reported by a low level on

the port-parity-error flag (PEFA, PEFB). Odd or even parity checking can be selected and the parity-error flags

can be ignored if this feature is not desired.