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SN74ACT8997 bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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SN74ACT8997 bảng dữ liệu(HTML) 7 Page - Texas Instruments |
7 / 28 page SN54ACT8997, SN74ACT8997 SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS SCAS157D – APRIL 1990 – REVISED DECEMBER 1996 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Exit1-IR, Exit2-IR These are temporary states that end the shifting process. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. The last shift occurs on the TCK cycle in which the TAP state changes from Shift-IR to Exit1-IR. TDO changes from the active state to the high-impedance state on the falling edge of TCK in Exit1-IR. Pause-IR The TAP can remain in this state indefinitely. The Pause-IR state suspends and resumes shift operations without loss of data. Update-IR In this state, the latches shadowing the instruction register are updated with the new instruction. instruction-register description The instruction register (IR) is an 8-bit serial register that outputs control signals to the device. Table 2 lists the instructions implemented in the ’ACT8997 and the data register selected by each instruction. The MSB of the IR is an even-parity bit. If the value scanned into the IR during Shift-IR does not contain even parity, an error signal (IRERR) is generated internally as shown in Table 3. The ’ACT8997 can be configured to output IRERR via DCO if the TAP enters the Pause-IR state. During the Capture-IR state, the IR status word is loaded.The IR status word contains information about the most recently loaded value of the instruction register and the logic level present at the DCI input. The IR status word is encoded as shown in Table 4. Figure 2 shows the order of scan for the IR. TDO Bit 7 (MSB) TDI or DTDI Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Figure 2. Instruction-Register Bits and Order of Scan |
Số phần tương tự - SN74ACT8997 |
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Mô tả tương tự - SN74ACT8997 |
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