MDA_ADCDS-1603.E06 Page 7 of 11

Timing

The ADCDS-1603 requires two independently operated signals to

accurately digitize the analog output signal from the CCD array.

The "Reference Hold" signal controls the operation of the internal

correlated double sampler (CDS) circuit. A logic "1" capture the value of

the CCD's reference signal. The Reference Hold Signal allows the user to

control the exact moment when the internal CDS is placed into the "hold"

mode. For optimal performance the internal CDS should be placed into the

"hold" mode once the reference signal has fully settled from all switching

Once the reference signal has been "held" and the pixel data portion

of the CCD's analog output signal appears at the ADCDS-1603's input,

the ADCDS-1603's correlated double sampler produces a "CDS Output"

signal (see Figure 8.) which is the difference between the "held"

reference level and its associated pixel data level (Reference-Pixel Data).

A/D conversion process can be initiated with the rising edge of the Start

Convert (Pin 25) signal.

Once the A/D conversion has been initiated, the Reference Hold (Pin 26)

can be placed back into the "Acquisition" mode in order to begin aquiring

the next reference level. For optimal performance the ADCDS-1603's

should be placed back into the "Aquisition" mode (Reference Hold to logic

"0") during the CCD's "Reference Quiet Time" ("Reference Quiet Time" is

defined as the period when the CCD's reference signal has settled from

all switching transients to the desired accuracy (see Figure 7.) Placing the

sample-hold back into the "aquisition" mode during the "Reference Quiet

Time" prevents the ADCDS-1603's internal amplifiers from unnecessarily

tracking (reproducing) the reset feedthrough glitch that occurs during the

CCD's reset to reference transition.

Disturbances to the system while the A/D is undergoing a conversion can

result in degradation of performance. It is therefore recommended that

both digital and analog signals (including the Reference/Pixel data inputs

to the ADCDS) not be allowed to switch during a time window of 150ns

to 300ns following the rising edge of the Start Convert command when

operating in the 0°C to 70°C temperature range, and from 140ns to

320ns for the extended temperature range. See timing Figure 7

"A/D Critical Conversion Window."

Note: At initial power-up, the first 186 conversions should be ignored.

Figure 7. Reference Hold Timing

Hold

Reset

Pixel Data

300 ns min.

150 ns max.

Reference

Reference

A/D Critical

Conversion

Window

"Quiet Time"

Acquisition

Time

Acquisition mode during

Reference “Quiet Time”

CCD

OUTPUT

REFERENCE

HOLD

START

CONVERT

Reference

ADCDS-1603

16-Bit, 2.3 Megapixels/Second

CCD Signal Processor

www.murata-ps.com