MDA_ADCDS-1603.E06 Page 3 of 11

TECHNICAL NOTES

1. Obtaining fully specified performance from the ADCDS-1603 requires

careful attention to pc-board layout and power supply decoupling.

The device's analog and digital grounds are connected to each other

internally. Depending on the level of digital switching noise in the overall

CCD system, the performance of the ADCDS-1603 may be improved by

connecting all ground pins (7,32,33,35, 37) to a large analog ground

plane beneath the package. The use of a single +5V analog supply for

2. Bypass all power supplies to ground with a 4.7μf ceramic capacitor in

parallel with a 0.1μf ceramic capacitor. Locate the capacitors as close to

the package as possible.

Figure 2a. Direct Mode

Figure 2b. Direct Mode

Figure 2c. Non-inverting Mode

3. Offset adjustment resistor (Figure 3), Rext (Figure 2b, 2c, & 2f),

ADCDS-1603 as possible.

4. A0 and A1 (pins 30, 31) should be bypassed with 0.1μf capacitors to

ground to reduce susceptibility to noise.

ADCDS-1603 Modes of Operation

The input amplifier stage of the ADCDS-1603 provides the designer with

a tremendous amount of flexibility. The architecture of the ADCDS-1603

allows its input-amplifier to be configured in any of the following

configurations:

When applying inputs that are less than 2.048Vp-p, a coarse gain

adjustment (applying an external resistor to pin 4) must be performed

to ensure that the full scale pixel data input signal (saturated signal)

(See figure 2b & 2C).

In all three modes of operation, the pixel data portion of the signal at

The ADCDS-1603 achieves its specified accuracies without the need for

external calibration. If required, the device's small initial offset error can be

reduced to zero using the OFFSET ADJUST (pin 2) feature (See figure 3). For

fine gain adjustment model, contact the factory.

Direct Mode (AC Coupled)

This is the most common input configuration as it allows the ADCDS-1603

to interface directly to the output of the CCD with a minimum amount of

analog "front-end" circuitry. This mode of operation is used with full-scale

pixel data input signals from 0.342Vp-p to 2.048Vp-p.

Figure 2a. describes the configuration for applications using a pixel data

input signal with a maximum amplitude of 0.342Vp-p. In this case the input

All input resistors having a 0.1% tolerance.

Figure 2b. describes the configuration for applications using a pixel

data input signal with an amplitude greater than 0.342Vp-p and less

than 2.048Vp-p. Using a single external series resistor, the coarse gain

of the ADCDS-1603 can be set. The coarse gain of the input amplifier

(1+(499/(100+Rext))) (all internal resistors having a 0.1% tolerance).

4

3

5

100

499

N.C.

= 2.048Vp-p

5k

0.01μF

22pf

4

3

5

100

499

N.C.

= 2.048Vp-p

0.01μF

Rext

5k

22pf

4

3

5

100

499

N.C.

= 2.048Vp-p

0.01μF

Rext

5k

22pf

Signal Timing

Conversion Rate (–40 to 125°C)

0.001

–

2.3

MHz

Conversion Time

434

–

–

nSec

Start Convert Pulse Width

20

50

140

nSec

Power Requirements

Power Supply Range

+5V A Supply

–5V Supply

+5V D Supply

+4.75

–4.75

–4.75

+5.0

–5.0

+5.0

+5.25

–5.25

+5.25

Volts

Volts

Volts

Power Supply Currents

+5V Supply

–5V Supply

+5V D Supply

–

–

+78

–47

+10

+83

–52

+12

mA

mA

mA

Power Dissipation

–

635

735

mW

Power Supply Rejection

(5%) @25°C

–

±0.01

±0.03

%FSR/%V

Environmental

Operating Temperature Range

ADCDS-1603

ADCDS-1603EX

0

–40

–

–

+70

+125

°C

°C

Storage Temperature

–65

–

+150

°C

Package Type

40-Pin, TDIP, 2.24" × 1.27" FR4 PCB

Weight

18.1 Grams

Pin Type

.020 Diameter Au Plate Phosphor Bronze

Cover

Tin Plate Steel

See Table 3.

See Timing Specs, Table 2.

See Technical Note: Optimal Performance.

CMOS Loading

A0, A1 = LO

ADCDS-1603

16-Bit, 2.3 Megapixels/Second

CCD Signal Processor

www.murata-ps.com