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SN74ABTH182652APM bảng dữ liệu(PDF) 3 Page - Texas Instruments |
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SN74ABTH182652APM bảng dữ liệu(HTML) 3 Page - Texas Instruments |
3 / 37 page SN54ABTH18652A, SN54ABTH182652A, SN74ABTH18652A, SN74ABTH182652A SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS SCBS167D – AUGUST 1993 – REVISED JULY 1996 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) In the test mode, the normal operation of the SCOPE ™ bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. Active bus-hold circuitry holds unused or floating data inputs at a valid logic level. The B-port outputs of ’ABTH182652A, which are designed to source or sink up to 12 mA, include 25- Ω series resistors to reduce overshoot and undershoot. The SN54ABTH18652A and SN54ABTH182652A are characterized for operation over the full military temperature range of – 55 °C to 125°C. The SN74ABTH18652A and SN74ABTH182652A are characterized for operation from – 40 °C to 85°C. FUNCTION TABLE (normal mode, each 9-bit section) INPUTS DATA I/O OPERATION OR FUNCTION OEAB OEBA CLKAB CLKBA SAB SBA A1 – A9 B1 – B9 OPERATION OR FUNCTION L H L L X X Input disabled Input disabled Isolation L H ↑↑ X X Input Input Store A and B data X H ↑ L X X Input Unspecified† Store A, hold B H H ↑↑ X‡ X Input Output Store A in both registers L XL ↑ X X Unspecified† Input Hold A, store B L L ↑↑ XX‡ Output Input Store B in both registers L L X X X L Output Input Real-time B data to A bus L L X X X H Output Input Stored B data to A bus H H X X L X Input Output Real-time A data to B bus H H X X H X Input Output Stored A data to B bus H L X X H H Output Output Stored A data to B bus and stored B data to A bus † The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs. ‡ Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered to load both registers. |
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