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SN74ABT574A bảng dữ liệu(PDF) 2 Page - Texas Instruments |
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SN74ABT574A bảng dữ liệu(HTML) 2 Page - Texas Instruments |
2 / 20 page SN54ABT574, SN74ABT574A OCTAL EDGETRIGGERED DTYPE FLIPFLOPS WITH 3STATE OUTPUTS SCBS191F − JANUARY 1991 − REVISED SEPTEMBER 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) The eight flip-flops of the SN54ABT574 and SN74ABT574A are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. terminal assignments 1234 A 1D OE VCC 1Q B 3D 3Q 2D 2Q C 5D 4D 5Q 4Q D 7D 7Q 6D 6Q E GND 8D CLK 8Q FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D OUTPUT Q L ↑ H H L ↑ LL L H or L X Q0 H X X Z logic diagram (positive logic) OE CLK 1D 1Q To Seven Other Channels C1 1 11 2 19 1D Pin numbers shown are for the DB, DW, FK, J, N, NS, PW, RGY, and W packages. SN74ABT574A . . . GQN OR ZQN PACKAGE (TOP VIEW) 1 234 A B C D E |
Số phần tương tự - SN74ABT574A |
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Mô tả tương tự - SN74ABT574A |
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