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SN74ABT374AN bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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SN74ABT374AN bảng dữ liệu(HTML) 4 Page - Texas Instruments |
4 / 7 page SN54ABT374, SN74ABT374A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS111G – FEBRUARY 1991 – REVISED JANUARY 1997 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C SN54ABT374 SN74ABT374A UNIT PARAMETER TEST CONDITIONS MIN TYP† MAX MIN MAX MIN MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5 VOH VCC = 5 V, IOH = –3 mA 3 3 3 V VOH VCC =4 5V IOH = –24 mA 2 2 V VCC = 4.5 V IOH = –32 mA 2* 2 VOL VCC =4 5V IOL = 48 mA 0.55 0.55 V VOL VCC = 4.5 V IOL = 64 mA 0.55* 0.55 V Vhys 100 mV II VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA IOZH VCC = 5.5 V, VO = 2.7 V 10‡ 10‡ 10‡ µA IOZL VCC = 5.5 V, VO = 0.5 V –10‡ –10‡ –10‡ µA Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA IO§ VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA V5 5 V I 0 Outputs high 250 250 250 µA ICC VCC = 5.5 V, IO = 0, VI =VCC or GND Outputs low 30 30 30 mA VI = VCC or GND Outputs disabled 250 250 250 µA ∆ICC¶ VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 1.5 1.5 1.5 mA Ci VI = 2.5 V or 0.5 V 3.5 pF Co VO = 2.5 V or 0.5 V 6.5 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ This data sheet limit may vary among suppliers. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ABT374 VCC = 5 V, TA = 25°C MIN MAX UNIT MIN MAX fclock Clock frequency 0 150 0 150 MHz tw Pulse duration CLK high or low 3.3 3.3 ns tsu Setup time before CLK ↑ Data high 2 2.5 ns tsu Setup time before CLK ↑ Data low 2 2.5 ns th Hold time after CLK ↑ Data high or low 2 2.5 ns |
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