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SN74ABT18652PM bảng dữ liệu(PDF) 3 Page - Texas Instruments |
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SN74ABT18652PM bảng dữ liệu(HTML) 3 Page - Texas Instruments |
3 / 11 page SN54ABT18652, SN74ABT18652 SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) In the test mode, the normal operation of the SCOPE ™ bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions such as parallel signature analysis on data inputs and pseudo-random pattern generation from data outputs. All testing and scan operations are synchronized to the TAP interface. Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. The SN54ABT18652 is characterized over the full military temperature range of – 55 °C to 125°C. The SN74ABT18652 is characterized for operation from – 40 °C to 85°C. FUNCTION TABLE (normal mode, each 9-bit section) INPUTS DATA I/O OPERATION OR FUNCTION OEAB OEBA CLKAB CLKBA SAB SBA A1 THRU A9 B1 THRU B9 OPERATION OR FUNCTION L H L L X X Input disabled Input disabled Isolation L H ↑↑ X X Input Input Store A and B data X H ↑ L X X Input Unspecified† Store A, hold B H H ↑↑ X‡ X Input Output Store A in both registers L XL ↑ X X Unspecified† Input Hold A, store B L L ↑↑ XX‡ Output Input Store B in both registers L L X X X L Output Input Real-time B data to A bus L L X L X H Output Input Stored B data to A bus H H X X L X Input Output Real-time A data to B bus H H L X H X Input Output Stored A data to B bus H L L L H H Output Output Stored A data to B bus and stored B data to A bus † The data output functions can be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs. ‡ Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both registers. |
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