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SM320C30HFGM40 bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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SM320C30HFGM40 bảng dữ liệu(HTML) 8 Page - Texas Instruments |
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8 / 47 page  SMJ320C30 DIGITAL SIGNAL PROCESSOR SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Pin Functions (Continued) PIN TYPE† DESCRIPTION CONDITIONS WHEN NAME QTY‡ TYPE† DESCRIPTION WHEN SIGNAL IS Z TYPE§ SERIAL PORT 0 SIGNALS CLKX0 1 I/O/Z Serial port 0 transmit clock. CLKX0 is the serial-shift clock for the serial port 0 transmitter. S R DX0 1 I/O/Z Data transmit output. Serial port 0 transmits serial data on DX0. S R FSX0 1 I/O/Z Frame synchronization pulse for transmit. The FSX0 pulse initiates the transmit-data process over DX0. S R CLKR0 1 I/O/Z Serial port 0 receive clock. CLKR0 is the serial-shift clock for the serial port 0 receiver. S R DR0 1 I/O/Z Data receive. Serial port 0 receives serial data on DR0. S R FSR0 1 I/O/Z Frame synchronization pulse for receive. The FSR0 pulse initiates the receive-data process over DR0. S R SERIAL PORT 1 SIGNALS CLKX1 1 I/O/Z Serial port 1 transmit clock. CLKX1 is the serial-shift clock for the serial port 1 transmitter. S R DX1 1 I/O/Z Data transmit output. Serial port 1 transmits serial data on DX1. S R FSX1 1 I/O/Z Frame synchronization pulse for transmit. The FSX1 pulse initiates the transmit-data process over DX1. S R CLKR1 1 I/O/Z Serial port 1 receive clock. CLKR1 is the serial-shift clock for the serial port 1 receiver. S R DR1 1 I/O/Z Data receive. Serial port 1 receives serial data on DR1. S R FSR1 1 I/O/Z Frame synchronization pulse for receive. The FSR1 pulse initiates the receive-data process over DR1. S R TIMER 0 SIGNALS TCLK0 1 I/O/Z Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an output, TCLK0 outputs pulses generated by timer 0. S R TIMER 1 SIGNALS TCLK1 1 I/O/Z Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an output, TCLK1 outputs pulses generated by timer 1. S R SUPPLY AND OSCILLATOR SIGNALS (see Note 1) VDD 4 I 5-V supply¶ IODVDD 2 I 5-V supply¶ ADVDD 2 I 5-V supply¶ PDVDD 1 I 5-V supply¶ DDVDD 2 I 5-V supply¶ MDVDD 1 I 5-V supply¶ VSS 4 I Ground DVSS 4 I Ground CVSS 2 I Ground † I = input, O = output, Z = high-impedance state, NC = no connect ‡ For GB package § S = SHZ active, H = HOLD active, R = RESET active ¶ Recommended decoupling capacitor is 0.1 µF. NOTE 1: CVSS, VSS, and IVSS are on the same plane. |
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