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MC-ACT-HDLC-VLOG bảng dữ liệu(PDF) 2 Page - Actel Corporation |
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MC-ACT-HDLC-VLOG bảng dữ liệu(HTML) 2 Page - Actel Corporation |
2 / 5 page Functional Description This core conforms to the appropriate standard(s). In general, standards do not define the internal user interface, only the external interfaces and protocols. Therefore, Avnet Memec has created a simple FIFO interface to this core for easy user connectivity. This document describes this Avnet Memec created interface. Please consult the appropriate standards document for all external signaling. TOP_SLAVE This is the top level of the core. Its only purpose is to serve as a container to instantiate the transmit & receive modules. TOP_SLAVE is also where the generics are located that configure the core. These parameters are then passed down to the TX & RX modules. TOP_EGR_SLAVE & TOP_ING_SLAVE These modules comprise the transmit and receive portions of the interface. They were developed so that they may be instantiated either separately in different FPGAs or together in one FPGA. They use the common sub-modules FIFO_16 & FIFO_8, for simplicity and reliability. EGR_UTOPIA3_SLAVE The Egress Slave is responsible for replying to polls from the master in order to receive cells from the master device. ING_UTOPIA3_SLAVE The Ingress Slave is responsible for responding to the master in order to send cells to the master device. FIFO_16 / FIFO_8 The FIFO module contains one FIFO per PHY polled (i.e. this module is instantiated N = number of PHY ports times in each direction. The FIFOs are created by utilizing the available RAM resources in the FPGA. Additionally, two FIFO_16 modules (and hence 2x the RAMs) are instantiated to create a 32-bit wide FIFO for the 32-bit mode, however 2x the cells can be buffered. The FIFO may be operated in synchronous (same clock for read & write) and asynchronous (different clocks for read & write) systems. Figure 1: Logic Symbol MDS8075 wr_data wr_flag wr_enb wr_clk rd_data rd_enb rd_clk rd_flag TxClk TxData TxEnb_n TxClav TxSoc TxPrty TxAddr reset_n fifo_16/fifo_8 top_egr_slave tx_utopia_slave top_egr_slave rx_utopia_slave top_ing_slave fifo_16/fifo_8 top_ing_slave RxClk RxData RxEnb_n RxClav RxPrty RxSoc RxAddr |
Số phần tương tự - MC-ACT-HDLC-VLOG |
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Mô tả tương tự - MC-ACT-HDLC-VLOG |
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