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STL-S3 bảng dữ liệu(PDF) 9 Page - Connor-Winfield Corporation

tên linh kiện STL-S3
Giải thích chi tiết về linh kiện  Stratum 3 Timing Module
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nhà sản xuất  CONNOR-WINFIELD [Connor-Winfield Corporation]
Trang chủ  http://www.conwin.com
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STL-S3 bảng dữ liệu(HTML) 9 Page - Connor-Winfield Corporation

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Preliminary Data Sheet #: TM055
Page 9 of 24
Rev: P00
Date: 5/17/04
© Copyright 2004 The Connor-Winfield Corp.
All Rights Reserved Specifications subject to change without notice
Master/Slave Operation
During master operation, the master pays no attention to the Slave Input reference other than monitoring it for qualification
purposes. If the slave unit is removed, there is no behavioral change in the master.
During slave operation, the slave module locks to the Slave Input reference from the master, and continually qualifies it. If the
slave module determines that the master input has gone out of range, the slave continues to lock to the master until it reaches the
end of its pull-in/hold-in range, which is approximately ±125 ppm. If the slave determines that the Slave Input frequency from the
master has been removed, the slave will use its internal priority table (which should be configured the same as the master module)
and configuration registers to begin locking to the highest priority qualified reference (or to the selected input reference if the master
unit was in manual mode). As soon as the Slave Input from the master returns, (after a 10 sec. minimum soak time) the slave will
begin locking to it.
When the module is in slave mode, the external indicator pins (Reference 1-Reference 6, Free Run, Hold Over) will remain
low, regardless of the mode. If the module is locked to or is attempting to lock to the master, the alarm indicator will be low. The
LOCK alarm works normally as long as the module is tracking the master. If the master is lost (due to LOR or out of tracking range),
and the module enters another mode, the alarm and LOCK indicators will both remain high (=1). The internal PLL status register
(0Eh) must be read to determine the current mode of operation of the module.
The goal of the slave is to maintain a zero-phase error with the Slave Input from the master. In order to accomplish this, the BW
during slave mode is increased so that the slave can respond very quickly to any change in the master's frequency to minimize the
phase difference between master and slave.
Master Mode
Slave Mode
Slave mode is selected
Master mode is selected
Master/Slave State Diagram
Figure 5


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