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AD5667BCPZ-REEL7 bảng dữ liệu(PDF) 9 Page - Analog Devices |
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AD5667BCPZ-REEL7 bảng dữ liệu(HTML) 9 Page - Analog Devices |
9 / 32 page AD5627R/AD5647R/AD5667R, AD5627/AD5667 Rev. 0 | Page 9 of 32 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 VOUTA 10 VREFIN 2 VOUTB 9 VDD 3 GND 8 SDA 4 LDAC 7 SCL 5 CLR 6 ADDR AD5627/ AD5667 TOP VIEW (Not to Scale) EXPOSED PAD TIED TO GND ON LFCSP PACKAGE. Figure 4. AD5627/AD5667 Pin Configuration 1 VOUTA 10 VREFIN/VREFOUT 2 VOUTB 9 VDD 3 GND 8 SDA 4 LDAC 7 SCL 5 CLR 6 ADDR AD5627R/ AD5647R/ AD5667R TOP VIEW (Not to Scale) EXPOSED PAD TIED TO GND ON LFCSP PACKAGE. Figure 5. AD5627R/AD5647R/AD5667R Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 2 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 3 GND Ground reference point for all circuitry on the part. 4 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the inputs have new data. This allows simultaneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low. 5 CLR Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part exits clear code mode on the falling edge of the 9th clock pulse of the last byte of valid write. If CLR is activated during a write sequence, the write is aborted. If CLR is activated during high speed mode the part will exit high speed mode. 6 ADDR Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address. 7 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit input register. 8 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 24-bit input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. 9 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 10 VREFIN/VREFOUT The AD56x7R have a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. (The internal reference and reference output are only available on R suffix versions.) The AD56x7 has a reference input pin only. |
Số phần tương tự - AD5667BCPZ-REEL7 |
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Mô tả tương tự - AD5667BCPZ-REEL7 |
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