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AD5422ACPZ bảng dữ liệu(PDF) 8 Page - Analog Devices

tên linh kiện AD5422ACPZ
Giải thích chi tiết về linh kiện  Single Channel, 12/16-Bit, Serial Input, Current Source & Voltage Output DAC
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AD5422ACPZ bảng dữ liệu(HTML) 8 Page - Analog Devices

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AD5412/AD5422
Preliminary Technical Data
Rev. PrF | Page 8 of 38
TIMING CHARACTERISTICS
AVDD = 10.8V to 40V, AVSS = -26.4V to -3V/0V, AVDD + |AVSS| < 52.8V, AGND = DGND = 0 V, REFIN= +5 V external;
DVCC = 2.7 V to 5.5 V, VOUT : RL = 1 kΩ, CL = 200 pF, IOUT : RL = 300Ω, HL = 50mH;
all specifications TMIN to TMAX, ±10 V / 0 to 24 mA range unless otherwise noted.
Table 4.
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
Write Mode
t1
33
ns min
SCLK cycle time
t2
13
ns min
SCLK low time
t3
13
ns min
SCLK high time
t4
13
ns min
LATCH delay time
t5
40
ns min
LATCH high time
t5
5
µs min
LATCH high time (After a write to the CONTROL register)
t6
5
ns min
Data setup time
t7
5
ns min
Data hold time
t8
40
ns min
LATCH low time
t9
20
ns min
CLEAR pulsewidth
t10
5
µs max
CLEAR activation time
Readback Mode
t11
82
ns min
SCLK cycle time
t12
33
ns min
SCLK low time
t13
33
ns min
SCLK high time
t14
13
ns min
LATCH delay time
t15
40
ns min
LATCH high time
t16
5
ns min
Data setup time
t17
5
ns min
Data hold time
t18
40
ns min
LATCH low time
t19
40
ns max
Serial output delay time (CL SDO4 = 15pF)
t20
33
ns max
LATCH rising edge to SDO tri-state
Daisychain Mode
t21
82
ns min
SCLK cycle time
t22
33
ns min
SCLK low time
t23
33
ns min
SCLK high time
t24
13
ns min
LATCH delay time
t25
40
ns min
LATCH high time
t26
5
ns min
Data setup time
t27
5
ns min
Data hold time
t28
40
ns min
LATCH low time
t29
40
ns max
Serial output delay time (CL SDO4 = 15pF)
1 Guaranteed by characterization. Not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 CL SDO = Capacitive load on SDO output.


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