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STV7697AWAF bảng dữ liệu(PDF) 7 Page - STMicroelectronics |
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STV7697AWAF bảng dữ liệu(HTML) 7 Page - STMicroelectronics |
7 / 15 page STV7697A 7/15 BLOCK DIAGRAM CIRCUIT DESCRIPTION The STV7697A contains all the logic and the pow- er circuits necessary to drive rows of a Plasma Display Panel (P. D. P.). The state of the displayed line is loaded into the shift register. Data are shift- ed at each low to high transition of the (CLK) shift clock. After 64 shifts the first bit is available at the serial output. This output can be used to cascade several drivers to perform any vertical resolution. The forward / reverse (F/R) input is used to select the direction of the shift register, data input/output status is set according to the selected direction. SIN, CLK, STB inputs are Smith trigger inputs . If not used on the appli- cation, F/R, BLK, POL logical inputs are internaly pulled to level ”1”. The maximum frequency of the shift clock is 20 MHz. All the data are memorized into the latch stage when the strobe input (STB) is pulled high. Blanking input (BLK) forces the power outputs to high level when pulled high with polarity input (POL) at high level and forced to low level with POL at low level. The level of the power output is inverted when the polarity command (POL) is pulled high. Sustain current must not be sunk in the power out- puttoVPP when the power supply is applied. VSSLOG and VSSSUB must be connected as close as possible to the logical reference ground of the application. Shift Register Truth Table F/R 87 64-BIT SHIFT REGISTER P1 P64 80 1 VSSP Pins 34-35-36-45-46 47-82-83-98-99 V CC Pins 41-90 V SSLOG Pins 39-40-42-94 SOUT (SIN) SIN (SOUT) STB BLK POL OUT1 OUT64 STV7697A 93 91 92 86 85 89 CLK V PP Pins 33-37-44-48 81-84-97-100 LATCH Q1 Q64 Q2 Q63 S64 S1 V CC V CC V CC V SSSUB Pins 38-43 V SSP V PP V SSP V PP Input Input /Outp ut Shift Register Fun ction F/R CLK SIN SOUT Output Q H Rise IN OUT Forward Shift H H or L IN OUT Steady L Rise OUT IN Reverse Shift L H or L OUT IN Steady 3 |
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