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I1LV3216ISA-7SI bảng dữ liệu(PDF) 9 Page - Renesas Technology Corp

tên linh kiện I1LV3216ISA-7SI
Giải thích chi tiết về linh kiện  32Mb Advanced LPSRAM (2M word x 16bit / 4M word x 8bit)
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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I1LV3216ISA-7SI bảng dữ liệu(HTML) 9 Page - Renesas Technology Corp

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R1LV3216R Series
Preliminary
REJ03C0367-0001, Rev.0.01, 2008.03.24
Page 9 of 16
Write Cycle
R1LV3216R**-5S
(Note 0)
R1LV3216R**-7S
Parameter
Symbol
Min.
Max.
Min.
Max.
Unit
Note
Write cycle time
tWC
55
-
70
-
ns
Address valid to end of write
tAW
50
-
65
-
ns
Chip select to end of write
tCW
50
-
65
-
ns
5
Write pulse width
tWP
40
-
55
-
ns
4
LB#, UB# valid to end of write
tBW
50
-
65
-
ns
Address setup time
tAS
0
-
0
-
ns
6
Write recovery time
tWR
0
-
0
-
ns
7
Data to write time overlap
tDW
25
-
35
-
ns
Data hold from write time
tDH
0
-
0
-
ns
Output enable from end of write
tOW
5
-
5
-
ns
2
Output disable to output in high-Z
tOHZ
0
20
0
25
ns
1,2
Write to output in high-Z
tWHZ
0
20
0
25
ns
1,2
Note0. 55ns parts can be supported under the condition of the input timing limitation toward SRAM on
customer’s system. Please contact our sales office in your region, in case of the inquiry for 55ns parts.
In case of tAA =70ns, tRC =70ns.
1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and
from device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB#
going low or UB# going low .
A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB#
going high or UB# going high. tWP is measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS1# going low or CS2 going high to end of write.
6. tAS is measured the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.


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