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MCF51JM64 bảng dữ liệu(PDF) 32 Page - Freescale Semiconductor, Inc |
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MCF51JM64 bảng dữ liệu(HTML) 32 Page - Freescale Semiconductor, Inc |
32 / 50 page MCF51JM128 ColdFire Microcontroller, Rev. 2 Preliminary Electrical Characteristics Freescale Semiconductor 32 2.12 SPI Characteristics Table 20 and Figure 14 through Figure 17 describe the timing requirements for the SPI system. Table 20. SPI Electrical Characteristic Num1 1 Refer to Figure 14 through Figure 17. C Characteristic2 2 All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. Symbol Min Max Unit 1 D Operating frequency Master Slave fop fop fBus/2048dc fBus/2 fBus/4 Hz 2 D Cycle time Master Slave tSCK tSCK 2 4 2048 — tcyc tcyc 3 D Enable lead time Master Slave tLead tLead — 1/2 1/2 — tSCKtS CK 4 D Enable lag time Master Slave tLag tLag — 1/2 1/2 — tSCKtS CK 5 D Clock (SPSCK) high time Master and Slave tSCKH 1/2 tSCK – 25 — ns 6 D Clock (SPSCK) low time Master and Slave tSCKL 1/2 tSCK – 25 — ns 7 D Data setup time (inputs) Master Slave tSI(M) tSI(S) 30 30 — — ns ns 8 D Data hold time (inputs) Master Slave tHI(M) tHI(S) 30 30 — — ns ns 9 D Access time, slave3 3 Time to data active from high-impedance state. tA 040 ns 10 D Disable time, slave4 4 Hold time to high-impedance state. tdis —40 ns 11 D Data setup time (outputs) Master Slave tSO tSO 25 25 — — ns ns 12 D Data hold time (outputs) Master Slave tHO tHO –10 –10 — — ns ns |
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