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MC145026P bảng dữ liệu(PDF) 8 Page - Freescale Semiconductor, Inc

tên linh kiện MC145026P
Giải thích chi tiết về linh kiện  Encoder and Decoder Pairs CMOS
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MC145026P bảng dữ liệu(HTML) 8 Page - Freescale Semiconductor, Inc

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MC145026, MC145027, MC145028 Technical Data, Rev. 4
8
Freescale Semiconductor
Operating Characteristics
3
Operating Characteristics
3.1
MC145026
The encoder serially transmits trinary data as defined by the state of the A1 - A5 and A6/D6 - A9/D9 input
pins. These pins may be in either of three states (low, high, or open) allowing 19,683 possible codes. The
transmit sequence is initiated by a low level on the TE input pin. Upon power-up, the MC145026 can
continuously transmit as long as TE remains low (also, the device can transmit two-word sequences by
pulsing TE low). However, no MC145026 application should be designed to rely upon the first data word
transmitted immediately after power-up because this word may be invalid. Between the two data words,
no signal is sent for three data periods (see Figure 11).
Each transmitted trinary digit is encoded into pulses (see Figure 12). A logic 0 (low) is encoded as two
consecutive short pulses, a logic 1 (high) as two consecutive long pulses, and an open (high impedance)
as a long pulse followed by a short pulse. The input state is determined by using a weak “output” device
to try to force each input high then low. If only a high state results from the two tests, the input is assumed
to be hardwired to VDD. If only a low state is obtained, the input is assumed to be hardwired to VSS. If both
a high and a low can be forced at an input, an open is assumed and is encoded as such. The “high” and
Figure 5. Output Transition Time
Figure 6. Din Rise and Fall Time
Figure 7. Encoder Clock Frequency
Figure 8. TE Pulse Width
Figure 9. Test Circuit
ANY OUTPUT
10%
90%
tTLH
tTHL
tf
tf
Din
10%
90%
VDD
VSS
t/fOSC
RTC
50%
tW
VDD
VSS
50%
TE
DEVICE
UNDER
TEST
OUTPUT
TEST POINT
CL*
* Includes all probe and fixture capacitance.


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