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MC145151-2 bảng dữ liệu(PDF) 4 Page - Freescale Semiconductor, Inc |
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MC145151-2 bảng dữ liệu(HTML) 4 Page - Freescale Semiconductor, Inc |
4 / 24 page MC145151-2 and MC145152-2 Technical Data, Rev. 5 4 Freescale Semiconductor MC145151-2 Parallel-Input (Interfaces with Single-Modulus Prescalers) N0 - N11 N Counter Programming Inputs (Pins 11 - 20, 22 - 25) These inputs provide the data that is preset into the ÷N counter when it reaches the count of zero. N0 is the least significant and N13 is the most significant. Pull-up resistors ensure that inputs left open remain at a logic 1 and require only an SPST switch to alter data to the zero state. T/R Transmit/Receive Offset Adder Input (Pin 21) This input controls the offset added to the data provided at the N inputs. This is normally used for offsetting the VCO frequency by an amount equal to the IF frequency of the transceiver. This offset is fixed at 856 when T/R is low and gives no offset when T/R is high. A pull-up resistor ensures that no connection will appear as a logic 1 causing no offset addition. OSCin, OSCout Reference Oscillator Input/Output (Pins 27, 26) These pins form an on-chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSCin to ground and OSCout to ground. OSCin may also serve as the input for an externally-generated reference signal. This signal is typically ac coupled to OSCin, but for larger amplitude signals (standard CMOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSCout. 1.2.2 Output Pins PDout Phase Detector A Output (Pin 4) Three-state output of phase detector for use as loop-error signal. Double-ended outputs are also available for this purpose (see φ V and φR). Frequency fV > fR or fV Leading: Negative Pulses Frequency fV < fR or fV Lagging: Positive Pulses Frequency fV = fR and Phase Coincidence: High-Impedance State φ R, φV Phase Detector B Outputs (Pins 8, 9) These phase detector outputs can be combined externally for a loop-error signal. A single-ended output is also available for this purpose (see PDout). If frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by φV pulsing low. φ R remains essentially high. If the frequency fV is less than fR or if the phase of fV is lagging, then error information is provided by φR pulsing low. φ V remains essentially high. If the frequency of fV = fR and both are in phase, then both φV and φR remain high except for a small minimum time period when both pulse low in phase. |
Số phần tương tự - MC145151-2 |
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Mô tả tương tự - MC145151-2 |
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