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FIN224AC bảng dữ liệu(PDF) 7 Page - Fairchild Semiconductor |
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FIN224AC bảng dữ liệu(HTML) 7 Page - Fairchild Semiconductor |
7 / 19 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN224AC Rev.1.1.5 7 LVCMOS Data I/O The LVCMOS input buffers have a nominal threshold value equal to half VDD. The input buffers are only oper- ational when the device is operating as a serializer. When the device is operating as a deserializer, the inputs are gated off to conserve power. The LVCMOS 3-STATE output buffers are rated for a source / sink current of approximately 0.5mA at 1.8V. The outputs are active when the DIRI signal and either S1 or S2 is asserted HIGH. When the DIRI signal and either S1 or S2 is asserted LOW, the bi-directional LVC- MOS I/Os is in a HIGH-Z state. Under purely capacitive load conditions, the output swings between GND and VDDP. When S1 or S2 initially transitions HIGH, the initial state of the deserializer LVCMOS outputs is zero. Unused LVCMOS input buffers must be either tied off to a valid logic LOW or a valid logic HIGH level to prevent static current draw due to a floating input. Unused LVC- MOS output should be left floating. Unused bi-directional pins should be connected to GND through a high-value resistor. If a FIN224AC device is configured as an unidi- rectional serializer, unused data I/O can be treated as unused inputs. If the FIN224AC is hardwired as a deseri- alizer, unused data I/O can be treated as unused outputs. |
Số phần tương tự - FIN224AC_08 |
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Mô tả tương tự - FIN224AC_08 |
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