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FIN212AC bảng dữ liệu(PDF) 2 Page - Fairchild Semiconductor |
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FIN212AC bảng dữ liệu(HTML) 2 Page - Fairchild Semiconductor |
2 / 23 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN212AC Rev. 1.0.6 2 Pin Definitions Pin I/O type # of Pins Description of Signals DP[1:12] CMOS-I/O 12 LV-CMOS Parallel I/O. Direction controlled by DIRI pin. CKREF CMOS-IN 1 LV-CMOS clock input and PLL reference. STROBE CMOS-IN 1 LV-CMOS strobe input for latching data into the serializer. CKP CMOS- OUT 1 LV-CMOS word clock output. DSO+(DSI-) (1) DSO-(DSI+) DIFF-I/O 2 CTL Differential serial I/O data signals. (2) DS(I)+: Positive signal of DS(I) pair; DS(I)-: Negative signal of DS(I) pair. CKSI+, CKSI- DIFF-IN 2 CTL Differential deserializer input bit clock. CKSI+: Positive signal of CKSI pair; CKSI-: Negative signal of CKSI pair. CKSO+, CKSO- DIFF-OUT 2 CTL Differential serializer output bit clock. CKSO+: Positive signal of CKSO pair; CKSO-: Negative signal of CKSO pair. S0, S1 CMOS-IN 1 DIRI=1: signals are used to define frequency range for the PLL. DIRI=0: Signals are used to define the edge rate of the deserializer parallel I/Os. PLL0(PWS0) CMOS-IN 1 DIRI=1: PLL0 signal is used to divide or adjust the serial frequency. DIRI=0: PWS0 signal is used to set the width of the CKP output pulse. PLL1(PWS1) CMOS-IN 1 DIRI=1: PLL1 Signal is used to divide the serial frequency. DIRI=0: PWS1 pin controls the output pulse width. TEST / (XTRM) CMOS_IN 1 DIRI=1: TEST=0, Normal Operation. DIRI=0: Termination enable functionality for deserializer. XTRM=0 Internal termination. XTRM=1 External termination required. Ground this pin for serializer. CTL_ADJ (GND) CMOS_IN 1 Adjusts CTL drive for serializer. Ground this pin for deserializer. DIRI IN 1 LV-CMOS Control Input. Used to control direction of data flow: DIRI= “1” Serializer, DIRI=“0” Deserializer /DIRO OUT 1 LV-CMOS Output. Inversion of DIRI in normal operation mode. VDDP Supply 1 Power supply for parallel I/O and translation circuitry. VDDS Supply 1 Power supply for core and serial I/O. VDDA Supply 1 Power supply for analog PLL circuitry. GND Supply 0 Ground center pad, ground D4, E3 and NCs for 42-ball BGA. Ground B5, C2, C4 for 36-ball BGA. Notes: 1. () Indicate deserializer functionality when DIRI=0. 2. The DS serial port pins are arranged such that when one device is rotated 180 degrees from the other device, the serial connections properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross. 3. All unused LV-CMOS input signals should be connected to GND or VDDP. Signals can be connected directly to the rail or through a resistor. 4. All unused LV-CMOS output signals should be allowed to float. |
Số phần tương tự - FIN212AC |
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Mô tả tương tự - FIN212AC |
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