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STP9NB50FP bảng dữ liệu(PDF) 1 Page - STMicroelectronics |
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1 / 9 page 1/9 May 2000 STP9NB50 STP9NB50FP N-CHANNEL 500V - 0.75 Ω - 8.6 A TO-220/TO-220FP PowerMesh ™ MOSFET s TYPICAL RDS(on) = 0.75 Ω s EXTREMELY HIGH dv/dt CAPABILITY s 100% AVALANCHE TESTED s VERY LOW INTRINSIC CAPACITANCES s GATE CHARGE MINIMIZED DESCRIPTION Using the latest high voltage MESH OVERLAY ™ process, STMicroelectronics has designed an ad- vanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprieraty edge termi- nation structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteris- tics. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SWITH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE ABSOLUTE MAXIMUM RATINGS ( •)Pulse width limited by safe operating area TYPE VDSS RDS(on) ID STP9NB50 500 V < 0.85 Ω 8.6 A STP9NB50FP 500 V < 0.85 Ω 4.9 A Symbol Parameter Value Unit STP9NB50 STP9NB50FP VDS Drain-source Voltage (VGS =0) 500 V VDGR Drain-gate Voltage (RGS =20 kΩ) 500 V VGS Gate- source Voltage ±30 V ID Drain Current (continuos) at TC =25°C 8.6 4.9 A ID Drain Current (continuos) at TC = 100°C 5.4 3.1 A IDM (q) Drain Current (pulsed) 34.4 34.4 A PTOT Total Dissipation at TC =25°C 125 40 W Derating Factor 1 0.32 W/ °C dv/dt (1) Peak Diode Recovery voltage slope 4.5 4.5 V/ns VISO Insulation Withstand Voltage (DC) - 2000 V Tstg Storage Temperature –65 to 150 °C Tj Max. Operating Junction Temperature 150 °C (1)ISD<9A, di/dt<200A/µ,VDD<V(BR)DSS,TJ<TJMAX INTERNAL SCHEMATIC DIAGRAM 1 2 3 1 2 3 TO-220 TO-220FP |
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