STn8811A12

Architecture overview

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2.4

ARM926EJ processor

The STn8811A12 CPU is an ARM926EJ reduced instruction set computer (RISC)

processor. This 32-bit processor core supports 32-bit ARM® and 16-bit Thumb instruction

sets, enabling the user to trade off between high performance and high code density.

The cached ARM CPU features a memory management unit (MMU) and is clocked at

393 MHz. It has a 32-Kbyte instruction cache and a 16-Kbyte data cache, and supports the

Jazelle™ extensions for Java acceleration.

It also includes an embedded trace module (ETM Medium+) for real-time CPU activity

tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed

trace mode, with normal or half-rate clock.

2.5

Embedded memory units

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32 Kbytes of public ROM (for boot purposes)

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64 Kbytes of secured ROM (for security purposes)

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40 Kbytes of public RAM

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16 Kbytes of secured RAM (for security code and/or data)

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1 Kbyte backup

2.6

Advanced security

The device contains 64 Kbytes of ROM and 16 Kbytes of RAM that are only accessible

when the system is in a trusted environment. An advanced security framework enables M-

commerce as well as authentication applications drawing on ST smartcard expertise:

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SHA-1/DES/3DES hardware accelerators

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True random number generator (RNG)

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Secured watchdog timer

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Unique die identification

2.7

Flexible static memory controller (FSMC)

The FSMC interfaces to off-chip multiplexed burst NOR Flash memory devices and NAND

Flash memory devices, and to Compact Flash/CF+ cards. The FSMC manages up to 3 chip-

selects of NOR Flash memories, and up to 2 chip-selects of NAND Flash memories or

Compact Flash/CF+ devices. The memory controller features error code correction

accelerated by hardware that reduces host CPU workload to support NAND Flash very fast

read/write transfers.

2.8

SDRAM memory controller (SDMC)

The SDMC is used to interface with double-data rate SDRAM (DDR-SDRAM) at 131 MHz.

The SDMC manages up to two chip-selects of 16-bit wide DDR-SDRAM. It can address up

to 128 Mbytes (1 Gbits) of SDRAM.