STn8810

Overview

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1.9

Real time clock (RTC)

The RTC provides a 1-second resolution clock. This keeps time when the system is inactive

and can be used to wake the system up when a programmed alarm time is reached. It has a

clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a

secured time update.

1.10

Timers

The STn8810 provides eight 16- or 32-bit (configurable) timers, as two groups of four. They

generate the periodic and timed interrupts required by OS services.

1.11

Watchdog timer

This OS resource is used to trigger a system reset in the event of software failure.

1.12

Vectored interrupt controller (VIC)

The VIC allows the OS interrupt handler to quickly dispatch interrupt service routines in

response to peripheral interrupts. There are 32 interrupt lines and the VIC uses a separate

bit position for each interrupt source. Software controls each request line to generate

software interrupts.

1.13

System and reset controller (SRC)

The SRC provides a control interface for clock generation components external to the

subsystem. It also controls system-wide and peripheral-specific energy management

features.

1.14

Direct memory access (DMA) controllers

Direct memory accesses can be employed for data transfers involving DMA peripherals. A

DMA controller services FIFO fill/empty requests from these peripherals immediately

without CPU interaction. Peripheral-to-peripheral and memory-to-memory DMAs are also

supported. A multichannel DMA controller is provided for efficient and concurrent data

transfers.

1.15

Universal asynchronous receivers-transmitters (UARTs)

The STn8810 provides three autobaud UARTs, one of which offers all modem control/status

signals. They are enhanced versions of the industry-standard 16C550 UART with a high

data rate up to 3.692 Mbit/s.