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LM3S600-IRN50-A0T bảng dữ liệu(PDF) 4 Page - Bookham, Inc.

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Giải thích chi tiết về linh kiện  Microcontroller
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LM3S600-IRN50-A0T bảng dữ liệu(HTML) 4 Page - Bookham, Inc.

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6.1.3
Power Control ........................................................................................................................... 51
6.1.4
Clock Control ............................................................................................................................ 51
6.1.5
System Control ......................................................................................................................... 54
6.2
Initialization and Configuration ................................................................................................... 54
6.3
Register Map ............................................................................................................................ 55
6.4
Register Descriptions ................................................................................................................ 56
7
Internal Memory ............................................................................................................... 103
7.1
Block Diagram ........................................................................................................................ 103
7.2
Functional Description ............................................................................................................. 103
7.2.1
SRAM Memory ........................................................................................................................ 103
7.2.2
Flash Memory ......................................................................................................................... 104
7.3
Flash Memory Initialization and Configuration ........................................................................... 106
7.3.1
Changing Flash Protection Bits ................................................................................................ 106
7.3.2
Flash Programming ................................................................................................................. 107
7.4
Register Map .......................................................................................................................... 107
7.5
Flash Register Descriptions (Flash Control Offset) ..................................................................... 108
7.6
Flash Register Descriptions (System Control Offset) .................................................................. 115
8
General-Purpose Input/Outputs (GPIOs) ....................................................................... 119
8.1
Functional Description ............................................................................................................. 119
8.1.1
Data Control ........................................................................................................................... 120
8.1.2
Interrupt Control ...................................................................................................................... 121
8.1.3
Mode Control .......................................................................................................................... 122
8.1.4
Pad Control ............................................................................................................................. 122
8.1.5
Identification ........................................................................................................................... 122
8.2
Initialization and Configuration ................................................................................................. 122
8.3
Register Map .......................................................................................................................... 123
8.4
Register Descriptions .............................................................................................................. 125
9
General-Purpose Timers ................................................................................................. 157
9.1
Block Diagram ........................................................................................................................ 158
9.2
Functional Description ............................................................................................................. 158
9.2.1
GPTM Reset Conditions .......................................................................................................... 158
9.2.2
32-Bit Timer Operating Modes .................................................................................................. 158
9.2.3
16-Bit Timer Operating Modes .................................................................................................. 160
9.3
Initialization and Configuration ................................................................................................. 164
9.3.1
32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 164
9.3.2
32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 165
9.3.3
16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 165
9.3.4
16-Bit Input Edge Count Mode ................................................................................................. 166
9.3.5
16-Bit Input Edge Timing Mode ................................................................................................ 166
9.3.6
16-Bit PWM Mode ................................................................................................................... 167
9.4
Register Map .......................................................................................................................... 167
9.5
Register Descriptions .............................................................................................................. 168
10
Watchdog Timer ............................................................................................................... 193
10.1
Block Diagram ........................................................................................................................ 193
10.2
Functional Description ............................................................................................................. 193
10.3
Initialization and Configuration ................................................................................................. 194
10.4
Register Map .......................................................................................................................... 194
October 01, 2007
4
Preliminary
Table of Contents


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