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1 / 11 page 1/11 November 2002 STP45NF3LL - STP45NF3LLFP STB45NF3LL N-CHANNEL 30V - 0.014 Ω - 45A TO-220 - TO220FP - D2PAK STripFET II™ POWER MOSFET (1) Starting Tj=25°C, ID= 22.5A, VDD=24V s TYPICAL RDS(on) = 0.014Ω @4.5V s OPTIMAL RDS(ON) x Qg TRADE-OFF @ 4.5V s CONDUCTION LOSSES REDUCED s SWITCHING LOSSES REDUCED s ADD SUFFIX “T4” FOR ORDERING IN TAPE & REEL DESCRIPTION This application specific Power MOSFET is the third genaration of STMicroelectronics unique “Single Feature Size ™” strip-based process. The resulting transistor shows the best trade-off be- tween on-resistance ang gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high effi- ciency are of paramount importance. APPLICATIONS s SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY DC/DC CONVERTERS ABSOLUTE MAXIMUM RATINGS (q) Pulse width limited by safe operating area TYPE VDSS RDS(on) ID STP45NF3LL STP45NF3LLFP STB45NF3LL 30 V 30 V 30 V <0.018 Ω <0.018 Ω <0.018 Ω 45 A 45 A 27 A Symbol Parameter Value Unit TO-220/D2PAK TO-220FP VDS Drain-source Voltage (VGS =0) 30 V VDGR Drain-gate Voltage (RGS =20kΩ) 30 V VGS Gate- source Voltage ± 16 V ID Drain Current (continuous) at TC = 25°C 45 27 A ID Drain Current (continuous) at TC = 100°C 32 19 A IDM ( ) Drain Current (pulsed) 180 108 A PTOT Total Dissipation at TC = 25°C 70 25 W Derating Factor 0.46 0.167 W/°C EAS (1) Single Pulse Avalanche Energy 241 mJ Viso Insulation Withstand Voltage (DC) -- 2500 V Tstg Storage Temperature –55 to175 °C Tj Max. Operating Junction Temperature D2PAK 1 3 1 2 3 TO-220 1 2 3 TO-220FP INTERNAL SCHEMATIC DIAGRAM |
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