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STA506A bảng dữ liệu(PDF) 5 Page - STMicroelectronics |
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STA506A bảng dữ liệu(HTML) 5 Page - STMicroelectronics |
5 / 14 page 5/14 STA506A Notes: 1. The following table explains the VLOW, VHIGH variation with VL Table 8. Note 2: see relevant Application Note AN1994 Table 9. Logic Truth Table (see fig. 4) VIN-L Low level input voltage VL/2 - 300mV V IIN-H Hi level Input current Pin Voltage = VL 1 µA IIN-L Low level input current Pin Voltage = 0.3V 1 µA IPWRDN-H Hi level PWRDN pin input current VL = 3.3V 35 µA VLOW Low logical state voltage VLow (pin PWRDN, TRISTATE) (note 1) VL = 3.3V 0.8 V VHIGH High logical state voltage VHigh (pin PWRDN, TRISTATE) (note 1) VL = 3.3V 1.7 V IVCC- PWRDN Supply CURRENT from Vcc in Power Down PWRDN = 0 3 mA IFAULT Output Current pins FAULT -TH-WARN when FAULT CONDITIONS Vpin = 3.3V 1 mA IVCC-hiz Supply Current from Vcc in Tri- state VCC = 30V; Tri-state = 0 22 mA IVCC Supply Current from Vcc in operation both channel switching) VCC =30V; Input Pulse width = 50% Duty; Switching Frequency = 384KHz; No LC filters; 50 mA IVCC-q Isc (short circuit current limit) (note 2) 46 8 A VUV Undervoltage protection threshold 7 V tpw_min Output minimum pulse width No Load 70 150 ns VL VLOW min VHIGH max Unit 2.7 0.7 1.5 V 3.3 0.8 1.7 V 5 0.85 1.85 V TRI-STATE INxA INxB Q1 Q2 Q3 Q4 OUTPUT MODE 0 x x OFF OFF OFF OFF Hi-Z 1 0 0 OFF OFF ON ON DUMP 1 0 1 OFF ON ON OFF NEGATIVE 1 1 0 ON OFF OFF ON POSITIVE 1 1 1 ON ON OFF OFF Not used Symbol Parameter Test conditions Min. Typ. Max. Unit Table 7. (continued) |
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