ST72321BAR6-AUTO datasheet(6/247 Pages) STMICROELECTRONICS

tên linh kiện	ST72321BAR6-AUTO

Giải thích chi tiết về linh kiện	8-bit MCU for automotive with 32 to 60 Kbyte Flash/ROM, ADC, 5 timers, SPI, SCI, I2C interface

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Contents

ST72321Bxxx-Auto

6/247

13.6

Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

13.7

16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

13.7.1

Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

13.7.2

Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

13.7.3

Control/status register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

13.7.4

Input capture 1 high register (IC1HR) . . . . . . . . . . . . . . . . . . . . . . . . . 121

13.7.5

Input capture 1 low register (IC1LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 122

13.7.6

Output compare 1 high register (OC1HR) . . . . . . . . . . . . . . . . . . . . . . 122

13.7.7

Output compare 1 low register (OC1LR) . . . . . . . . . . . . . . . . . . . . . . . 122

13.7.8

Output compare 2 high register (OC2HR) . . . . . . . . . . . . . . . . . . . . . . 122

13.7.9

Output compare 2 low register (OC2LR) . . . . . . . . . . . . . . . . . . . . . . . 123

13.7.10

Counter high register (CHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

13.7.11

Counter low register (CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

13.7.12

Alternate counter high register (ACHR) . . . . . . . . . . . . . . . . . . . . . . . . 123

13.7.13

Alternate counter low register (ACLR) . . . . . . . . . . . . . . . . . . . . . . . . . 124

13.7.14

Input capture 2 high register (IC2HR) . . . . . . . . . . . . . . . . . . . . . . . . . 124

13.7.15

Input capture 2 low register (IC2LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 124

14

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

14.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

14.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

14.3

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

14.3.1

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

14.3.2

Slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

14.3.3

Master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

14.3.4

Master mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

14.3.5

Slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

14.3.6

Slave mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

14.4

Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

14.5

Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

14.5.1

Master mode fault (MODF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

14.5.2

Overrun condition (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

14.5.3

Write collision error (WCOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

14.5.4

Single master systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

14.6

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

14.6.1

Using the SPI to wake up the MCU from Halt mode . . . . . . . . . . . . . . 135

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nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
STMicroelectronics	ST72321BARx	2Mb / 187P	32K to 60K dual voltage High Density Flash October 2008 Rev 5

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