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STWD100NWWY3F bảng dữ liệu(PDF) 5 Page - STMicroelectronics

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STWD100
Description
5/25
1
Description
The STWD100 watchdog timer circuits are self-contained devices which prevent system
failures that are caused by certain types of hardware errors (non-responding peripherals,
bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).
The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). The
input is used to clear the internal watchdog timer periodically within the specified timeout
period, twd (see Section 3: Watchdog timing). While the system is operating correctly, it
periodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is not
reset, a system alert is generated and the watchdog output, WDO, is asserted (see
Section 3: Watchdog timing).
The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable or
disable the watchdog functionality. The EN pin is connected to the internal pull-down
resistor. The device is enabled if the EN pin is left floating.
Figure 1.
SOT23-5 and SC70-5 (SOT323-5) package connections
1
VCC
GND
WDO
EN
AI12639b
2
3
5
4
WDI
Table 1.
SOT23-5 and SC70-5 (SOT323-5) pin description
Pin number
Name
Description
1WDO
Watchdog output
2
GND
Ground
3EN
Enable pin
4
WDI
Watchdog Input
5VCC
Supply voltage


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