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STTS424E02 bảng dữ liệu(PDF) 8 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  Memory module temperature sensor with a 2 Kb SPD EEPROM
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Serial communications
STTS424E02
8/51
Figure 1.
Logic diagram
1.
SDA and EVENT are open drain.
Note:
See Section 2.2: Pin descriptions on page 10 for details.
Figure 2.
DFN8 and TDFN8 connections (top view)
1.
SDA and EVENT are open drain.
Table 1.
Signal names
Pin
Symbol
Description
Direction
1
A0
Serial bus address selection pin. Can be tied to VSS or VDD.
Input
2
A1
Serial bus address selection pin. Can be tied to VSS or VDD.
Input
3
A2
Serial bus address selection pin. Can be tied to VSS or VDD.
Input
4VSS
Supply ground.
5SDA(1)
1.
SDA and EVENT are open drain.
Serial data.
Input/output
6
SCL
Serial clock.
Input
7
EVENT(1)
Event output pin. Open drain and active-low.
Output
8VDD
Supply power (2.7 V to 3.6 V).
AI12261
SDA(1)
VDD
STTS424E02
VSS
SCL
EVENT(1)
A2
A1
A0
1
SDA(1)
GND
SCL
EVENT(1)
A1
A0
VDD
A2
AI12262
2
3
4
8
7
6
5


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