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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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74V1T14 bảng dữ liệu(PDF) 1 Page - STMicroelectronics |
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74V1T14 bảng dữ liệu(HTML) 1 Page - STMicroelectronics |
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1 / 9 page  1/9 April 2004 s HIGH SPEED: tPD = 5.0ns (TYP.) at VCC =5V s LOW POWER DISSIPATION: ICC =1µA(MAX.) at TA=25°C s TYPICAL HYSTERESIS: Vh=700mV at VCC=4.5V s POWER DOWN PROTECTION ON INPUT s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|= IOL =8mA (MIN) at VCC =4.5V s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74V1T14 is an advanced high-speed CMOS SINGLE SCHMITT INVERTER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output. Power down protection is provided on input and 0 to 7V can be accepted on input with no regard to the supply voltage. This device can be used to interface 5V to 3V. Pin configuration and function are the same as those of the 74V1T04 but the 74V1T14 has hysteresis. This together with its schmitt trigger function allows it to be used on line receivers with slow rise/fall input signals. The input is equipped with protection circuits against static discharge, giving it ESD immunity and transient excess voltage. 74V1T14 SINGLE SCHMITT INVERTER PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE T & R SOT23-5L 74V1T14STR SOT323-5L 74V1T14CTR SOT323-5L SOT23-5L |
Số phần tương tự - 74V1T14_04 |
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Mô tả tương tự - 74V1T14_04 |
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