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STM1001R bảng dữ liệu(PDF) 4 Page - STMicroelectronics |
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4 / 14 page STM1001 4/14 OPERATION Reset Output The STM1001 MICROPROCESSOR RESET CIRCUIT asserts a reset signal to the MCU when- ever VCC goes below the reset threshold (VRST). RST is guaranteed valid down to VCC =1V (0° to 70°C). During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for the reset time-out period, trec. After this interval, RST returns high. If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays low for at least the reset time-out period. Any time VCC goes below the reset threshold, the internal timer clears. The reset timer starts when VCC returns above the reset threshold. The active-low reset (RST) is an open drain output. Negative-Going VCC Transients The STM1001 is relatively immune to negative-go- ing VCC transients (glitches). Figure 11., page 7 shows typical transient duration versus reset com- parator overdrive (for which the STM1001 will NOT generate a reset pulse). The graph was gen- erated using a negative pulse applied to VCC, starting at 0.5V above the actual reset threshold and ending below it by the magnitude indicated (comparator overdrive). The graph indicates the maximum pulse width a negative VCC transient can have without causing a reset pulse. As the magnitude of the transient increases (further be- low the threshold), the maximum allowable pulse width decreases. Any combination of duration and overdrive which lies under the curve will NOT gen- erate a reset signal. Typically, a VCC transient that goes 100mV below the reset threshold and lasts 20µs or less will not cause a reset pulse. A 0.1µF bypass capacitor mounted as close as possible to the VCC pin provides additional transient immunity. |
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