74LVQ74

2/13

Figure 2: Input And Output Equivalent Circuit

Table 2: Pin Description

Table 3: Truth Table

X : Don’t Care

Figure 3: Logic Diagram

This logic diagram has not be used to estimate propagation delays

PIN N°

SYMBOL

NAME AND FUNCTION

1, 13

1CLR, 2CLR

Asynchronous Reset -

Direct Input

2, 12

1D, 2D

Data Inputs

3, 11

1CK, 2CK

Clock Input (LOW to

HIGH, Edge Triggered)

4, 10

1PR, 2PR

Asynchronous Set - Direct

Input

5, 9

1Q, 2Q

True Flip-Flop Outputs

6, 8

1Q, 2Q

Complement Flip-Flop

Outputs

7

GND

Ground (0V)

14

Positive Supply Voltage

INPUTS

OUTPUTS

FUNCTION

CLR

PR

DCK

Q

Q

LH

X

X

LH

CLEAR

H

L

X

X

H

L

PRESET

LL

X

X

H

H

HH

L

L

H

HHH

H

L

HH

X

NO CHANGE