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74ALVCH32245LB bảng dữ liệu(PDF) 1 Page - STMicroelectronics |
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1 / 9 page 1/9 February 2002 s 3.6V TOLERANT INPUTS AND OUTPUTS s HIGH SPEED: tPD = 3.0ns (MAX.) at VCC = 3.0 to 3.6V tPD = 3.7ns (MAX.) at VCC = 2.3 to 2.7V s POWER DOWN PROTECTION ON INPUTS AND OUTPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V |IOH| = IOL = 8mA (MIN) at VCC = 2.3V s OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 3.6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 32245 s BUS HOLD PROVIDED ON BOTH SIDE s LATCH-UP PERFORMANCE EXCEEDS 300mA s ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74ALVCH32245 is a low voltage CMOS 32-BIT BUS TRANSCEIVER (3-STATE) fabricated with sub-micron silicon gate and five-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 V applications; it can be interfaced to 3.6V signal enviroment for both inputs and outputs. This IC is intended for two-ways asynchronous communication between data buses: the direction of data trasmission is determined by DIR input. Any nG contol output governs eight BUS TRANSCEIVERS. Output Enable input (nG) tied together gives full 32-bit operation. When nG is LOW, the output are enabled. When nG is HIGH, the output are in high impedance state so that the buses are effectively isolated. Bus hold on data inputs is provided in order to eliminate the need for external pull-up or pull-down resistor. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74ALVCH32245 LOW VOLTAGE CMOS 32-BIT BUS TRANSCEIVER (3-STATE) WITH 3.6V TOLERANTAT INPUTS AND OUTPUTS LOGIC DIAGRAM ORDER CODES PACKAGE TRAY T & R LFBGA96 74ALVCH32245LB 74ALVCH32245LBR LFBGA96 (Top and Bottom view) |
Số phần tương tự - 74ALVCH32245LB |
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Mô tả tương tự - 74ALVCH32245LB |
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