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SM320DM642AGDKI7EP bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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SM320DM642AGDKI7EP bảng dữ liệu(HTML) 4 Page - Texas Instruments |
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4 / 170 page  www.ti.com 1.3 Functional Block Diagram HPI32 OR HPI16 PCI-66 Test C64x DSP Core Data Path B B Register File B31−B16 B15−B0 Instruction Fetch Instruction Dispatch Advanced Instruction Packet Instruction Decode Data Path A A Register File A31−A16 A15−A0 Power-Down Logic .L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2 64 SDRAM FIFO SBSRAM SRAM L1P Cache Direct-Mapped 16K Bytes Total Control Registers Control Logic L1D Cache 2-Way Set-Associative 16K Bytes Total Advanced In-Circuit Emulation Interrupt Control TMS320DM642 Enhanced DMA Controller (EDMA) L2 Cache Memory 256kBytes PLL (x1, x6, x12) Timer 2 EMIF A ZBT SRAM Timer 1 Boot Configuration ROM/FLASH I/O Devices Video Port 2 (VP2) VCXO Interpolated Control Port (VIC) 8/10-bit VP1 McBSP1(A) Video Port 1 (VP1 ) AND McASP0 Data OR OR AND/OR EMAC MDIO OR GP0 I2C0 16 2 (B) 8/10-bit VP0 McBSP0(A) Video Port 0 (VP0) AND McASP0 Control OR OR Timer 0 SM320DM642-EP Video/Imaging Fixed Point Digital Signal Processor SGUS058B – JUNE 2007 – REVISED JANUARY 2008 Figure 1-1 shows the functional block diagram of the DM642 device. A. McBSPs: Framing Chips – H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs B. The Video Port 0 (VP0) peripheral is muxed with the McBSP0 peripheral and the McASP0 control pins. The Video Port 1 (VP1) peripheral is muxed with the McBSP1 peripheral and the McASP0 data pins. The PCI peripheral is muxed with the HPI(32/16), EMAC, and MDIO peripherals. For more details on the multiplexed pins of these peripherals, see the Device Configurations section of this data sheet. Figure 1-1. Functional Block Diagram SM320DM642 Video/Imaging Fixed-Point Digital Signal Processor 4 Submit Documentation Feedback |
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