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ADE7166ACPZF161 bảng dữ liệu(PDF) 11 Page - Analog Devices |
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ADE7166ACPZF161 bảng dữ liệu(HTML) 11 Page - Analog Devices |
11 / 148 page Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 11 of 148 TIMING SPECIFICATIONS AC inputs during testing are driven at VSWOUT – 0.5 V for Logic 1 and 0.45 V for Logic 0. Timing measurements are made at VIH min for Logic 1 and VIL max for Logic 0 as shown in Figure 2. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs as shown in Figure 2. CLOAD for all outputs = 80 pF, unless otherwise noted. VDD = 2.7 V to 3.6 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. CLOCK INPUT (External Clock Driven XTAL1) Parameter 32.768 kHz External Crystal Min Typ Max Unit tCK XTAL1 Period 30.52 μs tCKL XTAL1 Width Low 6.26 μs tCKH XTAL1 Width High 6.26 μs tCKR XTAL1 Rise Time 9 ns tCKF XTAL1 Fall Time 9 ns 1/tCORE Core Clock Frequency1 TBD TBD 4.096 MHz 1 ADE75xx/ADE71xx internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 12.58 MHz internal clock for the system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR. DVDD – 0.5V 0.45V 0.2DVDD + 0.9V TEST POINTS 0.2DVDD – 0.1V VLOAD – 0.1V VLOAD VLOAD + 0.1V TIMING REFERENCE POINTS VLOAD – 0.1V VLOAD VLOAD – 0.1V Figure 2. Timing Waveform Characteristics |
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