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MC74HCXXXAD bảng dữ liệu(PDF) 1 Page - Motorola, Inc |
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MC74HCXXXAD bảng dữ liệu(HTML) 1 Page - Motorola, Inc |
1 / 6 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1 REV 6 © Motorola, Inc. 1995 10/95 Quad 2-Input NAND Gate with Schmitt-Trigger Inputs High–Performance Silicon–Gate CMOS The MC54/74HC132A is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC132A can be used to enhance noise immunity or to square up slowly changing waveforms. • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Complexity: 72 FETs or 18 Equivalent Gates LOGIC DIAGRAM A1 B1 Y1 3 2 1 PIN 14 = VCC PIN 7 = GND Y = AB A2 B2 Y2 6 5 4 A3 B3 Y3 8 10 9 A4 B4 Y4 11 13 12 MC54/74HC132A FUNCTION TABLE PIN ASSIGNMENT Inputs Output A B Y L L H L H H H L H H H L 11 12 13 14 8 9 10 5 4 3 2 1 7 6 B3 Y4 A4 B4 VCC Y3 A3 A2 Y1 B1 A1 GND Y2 B2 D SUFFIX SOIC PACKAGE CASE 751A–03 N SUFFIX PLASTIC PACKAGE CASE 646–06 MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD Ceramic Plastic SOIC 1 14 1 14 J SUFFIX CERAMIC PACKAGE CASE 632–08 1 14 ORDERING INFORMATION |
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