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3 / 320 page 3/320 Table of Contents 9 3.5 EEPROM . .... .. . . . . . . . . .... . ... .. . . . . .... .... .. . .... .. . . . . . . ... .. . .... 53 3.5.1 Hardware EEPROM Emulation . . . ... .. ... .. .. ... .. .. ... .. .. .... . . ... .. 53 3.5.2 EEPROM Update Operation . . . . . . . . . . . . . . . .... .... ... . . . . . . . . ... .. . . . 54 3.6 PROTECTION STRATEGY . .... . ... .. . . . . .... .... .. . . . . . . . . . . . . . ... .. . .... 55 3.6.1 Non Volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . ... .. .. ... 55 3.6.2 Temporary Unprotection . . . . . . . . . . . . .... .... .. . . . . . . . . . . . . . ... .. . .... 57 3.7 FLASH IN-SYSTEM PROGRAMMING . . . . . . . .... ... . . . . . . . . . . . . . . . . . . . . ... .. 57 3.7.1 First Programming of a virgin Flash . . . . . . . . . . . . . . . . . . . . . . .... . ... .. . . ... 57 4 REGISTER AND MEMORY MAP .... .. . . . . . . . . .... . ... .. .. .. . .... ... . . . . . . . . . . . . 59 4.1 INTRODUCTION . . . . . . . . . . . . . .... . . ... .. ... .. .. . . . . . . . ... .. .. .... . . ... .. 59 4.2 MEMORY CONFIGURATION . . . . . . . . . . . . . .... . . . . .. . . . . . . . . . . . . . ... .. . .... 59 4.3 ST92F120 REGISTER MAP . . . . . . . . . . . . . . . . ... . . . . . . . . . .... ... . . . . . . . . . . . . 62 5 INTERRUPTS . . .... .. . . . . . . . . .... . ... .. . . . . .... .... .. . .... .. . . . . . . ... .. . . . . . 72 5.1 INTRODUCTION . . . . . . . . . . . . . .... . . ... .. ... .. .. . . . . . . . ... .. .. .... . . ... .. 72 5.2 INTERRUPT VECTORING .... .. . .... .. . .... . ... .. .. .. .... . . . ... . . . . . . . . . . 72 5.2.1 Divide by Zero trap . . . . . . . . . . . . . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . . 72 5.2.2 Segment Paging During Interrupt Routines . . . . . . . . . . . .... . . . ... . . . . . . . . . . 73 5.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.4 PRIORITY LEVEL ARBITRATION . . . . . . ... .. ... .. .. ... .. .. ... .. .. .... . . ... .. 73 5.4.1 Priority level 7 (Lowest) . . . .... . . ... .. ... .. .. . . . . . . . ... .. .. .... . . ... .. 73 5.4.2 Maximum depth of nesting . . . . . . . . . . . . . ... . . . . . . . . . .... ... . . . . . . . . . . . . 73 5.4.3 Simultaneous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.4.4 Dynamic Priority Level Modification . . . . . .... ... . . . . . . . . . . . . . . . . . .. . ... .. 74 5.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . .... . ... .. . . . . .... . . . ... . . . . . . . . . . 74 5.5.1 Concurrent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.5.2 Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .... .. . . . . . . . . . . 77 5.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . .... .... ... . . . . . . . . ... .. . . . 79 5.6.1 Standard External Interrupts . . . . . . . . . . . ... . . . . . . . . . .... ... . . . . . . . . . . . . 79 5.7 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . .... ... . . . . . . . . . . . . . . . . . . . . ... .. 81 5.8 ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . ... .. 81 5.9 INTERRUPT RESPONSE TIME . .... . . ... .. .... ... . . . . . . . . . . . . . . . . . . . . ... .. 82 5.10 INTERRUPT REGISTERS . . .... . ... .. . . . . .... .... .. . . . . . . . . . . . . . ... .. . .... 83 5.11 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU) . . . . . . . . . . . . . . . . . . 86 5.11.1Introduction . . . . .... . . .. .. .. .. . . . . . . . . . . . . . ... . . . . . . . . . ... .. .. ... .. 86 5.11.2Main Features . . . . . . . . . . . . . . . . . . . . .... . . . ... . . . . . . . . . . . . . ... .. . . .. . 86 5.11.3Functional Description . . . . . . . .... . ... .. .. .. . . . . . . . . . . . . ... . . . .... . ... 87 5.11.4Programming Considerations . . . . . . . . . . ... . . . . . . . . . .... ... . ... . . .. .. .. 90 5.11.5Register Description . . . . . . . . . .... . ... .. .. .. . . . . . . . . . . . . ... . . . .... . ... 91 6 ON-CHIP DIRECT MEMORY ACCESS (DMA) . . . . . . . ... . . . . . . . . . .... ... . . . . . . . . . . . . 94 6.1 INTRODUCTION . . . . . . . . . . . . . .... . . ... .. ... .. .. . . . . . . . ... .. .. .... . . ... .. 94 6.2 DMA PRIORITY LEVELS . . . .... . ... .. . . . . .... .... .. . .... .. . . . . . . ... .. . .... 94 6.3 DMA TRANSACTIONS . . . . . . . . . . . . . . ... .. ... .. .. ... .. .. ... .. .. .... . . ... .. 95 6.4 DMA CYCLE TIME . . . . . . . . . . . . . . . .... . ... .. .. .. . . . . . . . . . . . . ... . . . .... . ... 97 6.5 SWAP MODE . . . . . . . . . . . . .... . ... .. . . . . .... .... .. . .... .. . . . . . . ... .. . .... 97 6.6 DMA REGISTERS . . . . . . . . . . . . .... . . ... .. .... ... . . . . . . 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