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ST62E18C bảng dữ liệu(PDF) 5 Page - STMicroelectronics |
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ST62E18C bảng dữ liệu(HTML) 5 Page - STMicroelectronics |
5 / 82 page 5/82 ST62T18C/E18C 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62T18C and ST62E18C devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which are targeted at low to medium complexity applications. All ST62xx de- vices are based on a building block approach: a common core is surrounded by a number of on- chip peripherals. The ST62E18C is the erasable EPROM version of the ST62T18C device, which may be used to em- ulate the ST62T18C device, as well as the respec- tive ST6218C ROM devices. Figure 1. Block Diagram TEST NMI INTERRUPT PROGRAM PC STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 POWER SUPP LY OSCILLATOR RESET DATA ROM USER SELECTABLE DATA RAM PORT A PORT B TIMER DIGITAL 8 BIT CORE TEST/VPP 8-BIT A/D CONVERTER PA1 / 20 mA Sink VDD VSS OSCin OSCout RESET WATCHD OG Memory AUTORELOA D TIMER 192 Bytes 7948 bytes PA2/ARTIMo ut / 20 mA Sink PA3/ART IMin/ 20 mA Sink PA4..PA 5/20 mA Sink PB4..PB6/Ain PORT D PD6,PD7/Ain PD4/Ain/RXD1 PD5/Ain/TXD1 (VPP on EPROM/OTP versions only) TIMER VR01823F UART 5 |
Số phần tương tự - ST62E18C |
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Mô tả tương tự - ST62E18C |
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