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ST5451D bảng dữ liệu(PDF) 10 Page - STMicroelectronics |
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ST5451D bảng dữ liệu(HTML) 10 Page - STMicroelectronics |
10 / 34 page MONR2 Monitor Receive Register 2 After reset FFH (GCI and TE mode only) The value read from MONR2 gives the value of the byte received from M channel in 2nd GCI channel. TSR Time Slot Register After reset 00 TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 In GCI mode (MDS1= 1 in CF Register) a) CCS=1 in CF Reg. (64 Kbit/s) Then: TSR2 indicates B1 or B2 TSR4/7 indicate position of GCI channel b) CCS=0 in CF Reg. (16 Kbit/s) Then: TSR4/7 indicate position of GCI and its D channel In Multiplexed Mode (MDS1=0 in CF Register) a) CCS=1 in CF Reg. (64 Kbit/s) Then: TSR2/7 indicate channel position in the 64 time slots multiplex b) CCS=0 in CF Reg. (16 Kbit/s) Then: TSR0/7 indicate channel position in the 256 time slots multiplex. CA Configurationn Register A After reset 00 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 CA0 SAPI 0 is recognized CA0 = 1 CA1 SAPI 63 CA1 = 1 CA2 SAPI x CA2 = 1 CA3 SAPI y CA3 = 1 CA4 TEI 127 CA4 = 1 CA5 TEI z CA5 = 1 CA6 TEI t CA6 = 1 CA7 Address filter active CA7 = 1 CB Configuration register B After reset 00 Content of CB indicate SAPI x value High Order 6 Bits SAPI 0 0 CC Configuration Register C After reset 00 Content of CC indicate SAPI y value High Order 6 Bits SAPI 0 0 N (number of bytes in the frame received without CRC) Counter n (number of 32 bytes blocks received ) 765 432 1 0 Nn m n 1 Min 000 00001 0 2 000 00010 0 3 000 00011 0 30 000 11110 0 31 000 11111 0 32 001 00000 1 33 001 00001 1 62 001 11110 1 63 001 11111 1 64 010 00000 2 222 110 11110 6 223 110 11111 6 224 111 11111 7 256 111 00000 7 257 111 00001 7 - 111 - 7 TABLE 3 ST5451 10/34 |
Số phần tương tự - ST5451D |
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Mô tả tương tự - ST5451D |
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